Kaiserslautern, Germany, January 14, 2025 - Creonic GmbH, the leading provider of cutting-edge communications IP cores, ...
The next-generation UCIe physical layer IP, based on TSMC's N4 process, is expected to finalize its design later this year, ...
This milestone marks a significant achievement in ensuring seamless integration and reliable data transfer between the two ...
YorChip, Inc. and Chipcraft announce development of a low cost, low power 8 bit 200Ms/s ADC Chiplet. Currently no ultra-low ...
Lonquan 560 SoCs leverage Ceva-SensPro Vision AI DSP to advance ADAS capabilities amidst China's rapidly growing EV market ...
QUALITAS SEMICONDUCTOR, a leading provider of high-speed interconnect solutions, has announced the supply of its 4nm PCIe 6.0 ...
The JESD204C standard enables establishing high-speed serial links between a Controller and ADC and DAC converters. JESD204C ...
The MUSBFPHY IP PHY from Mentor Graphics?is an on-chip transceiver for USB On-The-Go (OTG) that complies with both the USB standard for Full-Speed functions and the OTG supplement to the USB 2.0 ...
Serial NOR Flash Memory Model provides an smart way to verify the Serial NOR Flash component of a SOC or a ASIC. The SmartDV s Serial NOR Flash memory model is fully compliant with standard Serial NOR ...
The Xilinx® Zynq® UltraScale+™ RFSoC family integrates the key subsystems required to implement a complete software-defined radio including direct RF sampling data converters, enabling CPRI and ...
This 28nm GPIO is designed for high-speed (>150MHz output, >250MHz input) applications. The IO operates at either 1.8V or 3.3V and can dynamically switch between these voltages during operation. The ...
SPI (Serial Peripheral Interface) is the serial synchronous communication protocol developed by SPI Block Guide V04.01. SPI VIP can be used to verify Master or Slave device following the SPI basic ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback