EDN

Latches and timing closure: a mixed bag

Digital blocks contain combinational andsequential circuits. Sequential circuits are thestorage cells with outputs that reflect the pastsequence of their input values, whereas the outputof the ...
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Hackaday

AVR Configurable Custom Logic As A Frequency Divider At 4x Chip’s Clock Speed

What a time to be alive when you can find inexpensive microcontrollers that come with programmable(ish) logic that can operate independently of the system clock. [David Johnson-Davies] recently built ...
Design-Reuse

Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems

Using pulsed latches instead of flip-flops is a solution that has been thoroughly studied for its advantages in speed, density, and power consumption reduction [1] [2]. Even so, this solution has not ...
Design-Reuse

Logic design optimization takes a quantum leap with Dolphin Integration's standard cell library enriched with pulsed latches

Meylan, France – July 13, 2012. Dolphin Integration announces a breakthrough solution enriching SESAME 6-track library, which can be used for helping logic designers reach 10% to 20% density gains ...
Hackaday

Learn Flip Flops With (More) Simulation

In the previous installment, we talked about why flip flops are such an important part of digital design. We also looked at some latch circuits. This time, I want to look at some actual flip ...
Semiconductor Engineering

DFT and Clock Gating

Design for test (DFT) is also important in low-power design. To increase test coverage, ensure that the clock-gating logic inserted by the low-power engine is controllable and observable. First, ...