EDN

Designers stand up for gate-level simulation

SANTA CRUZ, Calif. — In theory, static timing analysis and formal verification should render gate-level simulation unnecessary. But in reality, it's unavoidable, according to a number of engineers who ...
EDN

Gate level simulations: verification flow and challenges

Simulations are an important part of the verification cycle in the process of hardware designing. It can be performed at varying degrees of physical abstraction: In many companies RTL simulations is ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Electronic Design

Instant "Replay" Comes To Timing Simulation

Novas Software's Siloti Replay technology streamlines the process of detecting, isolating, and fixing the source of timing problems using gate-level simulation. The module yields significantly faster ...
Design-Reuse

Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification

ANDOVER, Mass.-- March 23, 2012--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its revolutionary X verification solution, ...
Semiconductor Engineering

Low Power Simulation

Once in a while I’m asked if it’s necessary to check power and ground connections with VDD/VSS-aware simulation on a physical (PG) netlist. The short answer is: “No, as long as you have run LP ...