With the increasing size and complexity of FPGA devices, there is a need for more efficient verification methods. Timing simulation can be the most revealing verification method; however, it is often ...

Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the ...

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening ...

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.

It’s no secret that hardware is the new currency in the chip world. It’s no longer the case that the semiconductor industry is in the hands of traditional semiconductor giants; an increasing number of ...

As autonomous systems, connected devices, and AI technologies continue to come online, engineering teams are finding it more difficult to rely on traditional development methods. As the sophistication ...